Optimization of guard rings construction and epitaxial film resistivity of power n-channel DMOS-transistor

Abstract

Powerful n-channel DMOS-transistor with drain-source breakdown voltage U_{ds br} value over 800 V and thresh-old voltage from 2 to 5 V was considered in this paper. One or more guard rings are formed on perimeter of such transistor for the breakdown voltage raising. The optimal guard rings construction was described and resistivity value of epitaxial film ρ_v was determined for obtaining required transistor U_{ds br} value. The regression model was built, with the help of which the most optimal construction variants of guard rings of investigated transistor and resistivity value of epitaxial film, were selected. It was established that the five-dimensional polynomial of second order using as regression model allowed choosing the optimal topological spaces values in the guard rings area and ρ_v value which made it possible to obtain required U_{ds br} values of the transistor. Experimental values of transistor drain-source breakdown voltage were 876 and 875 V, but calculated values (at identical parameters of definitional regression model) were 874 and 880 V, accordingly, that were errors of 0.23 % and 0.57 %, i. e. made model fits well with experimental data. It was established that ρ_v makes contribution to breakdown voltages values of the transistor that is more substantial than parameters of guard rings construction. This NDMOS-transistor was manufactured under production conditions of OJSC INTEGRAL” – “INTEGRAL” Holding Managing Company according to the technological route developed by the author. Such device is used in various electronic devices for energetics, in mobile phones, as part of high-voltage integrated circuits of AC/DC- and DC/DC-converters and high-voltage, high-stable LED-drivers.